Intel dives into the ultra-low power pool

The chipmaking giant announced on Monday a new technique that it said could help cut back on wasted battery power in cell phones and mobile devices by as much as 1,000 times current levels.

Active computing accounts for only half the power Intel processors use. The other half is gobbled up by a leakage current in transistors that exists when a machine is in a low-level sleep state, Intel said.

The new version of the company's 65-nanometer wafer-making process, internally known as P1265, is better than Intel's current process at helping prevent the extra power from being sapped from the battery, the chipmaker said.

The new process is scheduled to affect a large percentage of Intel chips in 2007, coinciding with the release of the company's next-generation of processors like Merom, which are designed to consume a tenth of the power that Intel's Pentium mobile chips use.

"With the number of transistors on some chips exceeding 1 billion, it is clear that improvements made for individual transistors can multiply into huge benefits for the entire device," said Mark Bohr, an Intel senior fellow.

Creating more efficient low-power processors was one of the main themes expressed by Intel executives at the Intel Developer Forum in San Francisco this August. During his keynote, CEO Paul Otellini announced a goal that by the end of the decade, Intel would have another new architecture running x86 code at as low as a half a watt--that is, about a tenth the demand of the lowest-power version currently available.

It's an important step for the company's drive to put more of its processors in mobile handheld communications equipment, said Kevin Krewell, a principal analyst at semiconductor research firm In-Stat.

"It's not the first time that this technique has been done, but it's the first time that Intel has put out a process for these characteristics," Krewell said.

Texas Instruments and Freescale Semiconductor are among other companies in the chipmaking industry that are working on 65-nanometer transistor leakage issues. Historically, chipmakers have toyed with idle and sleep modes, clock gating and dynamic voltage to conserve battery life.

TI first introduced technology elements of its SmartReflex technologies at the 90-nanometer process node and is now testing the same techniques at the 65-nanometer process level in its family of OMAP 2 chips.

Earlier this year, Freescale licensed Virage Logic's technology for use in Freescale's upcoming cellular baseband products.

Bohr said Intel's new process is distinctive in that it uses thinner copper connections between transistors to help increase density and cut back on three major types of transistor leakage: subthreshold, junction and gate oxide.

"About two years ago, the Intel process and development groups decided to find out if they could expand the space or the scope that 65-nanometer technology could serve and make adjustments so it could make a chip with extra-low leakage," Bohr said.

The new process uses many of the same components as Intel's current road map for its 65-nanometer process. Intel said it's on track to produce 300-millimeter wafers based on its original 65-nanometer designs later this year.

The new ultralow-voltage process will debut in Intel's D1D fabrication plant in Oregon, which is already running tests of the company's first generation of wafers built using the 65-nanometer process. Fab 12, in Arizona, will be the second facility to produce the silicon later this year. Intel's fabrication plant in Ireland, Fab 24, will come online with the new process in the first quarter of 2006, Bohr said.