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Intel at chip conference: More cores, less power

Intel will have a lot to say at International Solid-State Circuits Conference, spanning the spectrum of silicon from mobile to server processors.

Brooke Crothers Former CNET contributor
Brooke Crothers writes about mobile computer systems, including laptops, tablets, smartphones: how they define the computing experience and the hardware that makes them tick. He has served as an editor at large at CNET News and a contributing reporter to The New York Times' Bits and Technology sections. His interest in things small began when living in Tokyo in a very small apartment for a very long time.
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Brooke Crothers
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Intel will have a lot to say at the International Solid-State Circuits Conference, spanning the spectrum of silicon from mobile to server processors. Here are a few of the highlights from abstracts of Intel sessions at the ISSCC, which kicks off Sunday in San Francisco.

Nehalem, currently marketed as the Core i7, will scale down to sub-10-watt chips--that's ultraportable notebook (think MacBook Air) territory:

  • "A family of next-generation IA processors...The family has a coherent point-to-point link and integrates memory controller, power-management microcontroller and power-gate transistors and scales from sub-10 to 130W in mobile, desktop and server applications."

Part of the message will be more brute-force silicon: more processor cores, bigger caches--especially for Intel's high-end Xeon processor line:

  • 8-core Xeon processor (aka Nehalem-EX): "An 8-core 16-thread enterprise Xeon processor has 2.3B transistors in 9M 45nm CMOS...operation up to 6.4GT/s...Core and cache shut-off techniques are used to minimize leakage." (Note: '9M" means nine metal layers; "GT/s" is giga-transfers per second.)
  • 6-core Xeon (aka Dunnington): "A monolithic 6-core Xeon processor has 1.9B transistors in 9M 45nm CMOS with a 9MB L2 and 16MB L3 cache and exceeds 1M transactions/minute TPCC in 8-socket configuration. The FSB (Front-Side Bus) I/O circuits are implemented in the center of the die to reduce I/O latency. A low-leakage process variant with cache-sleep and shut-off modes enables low-power 6-core 65W and 4-core 50W variants."

And let's try not to forget Itanium--Intel's, some would say, ill-fated silicon for very-high-end severs:

  • "The clock system for a 700mm2 65nm quad-core Itanium processor has a cascaded PLL (phase locked loop) architecture and enables dynamic frequency switching."

Intel will also present on graphics-related mobile silicon:

  • "A 4-way SIMD (Single Instruction Multiple Data) accelerator for power-constrained microprocessors fabricated in 1.1V, 45nm CMOS occupies 0.081mm2...Enables mode-dependent power savings while achieving wide operating range (1.3V to 230mV) with 2.3GHz, 161mW operation at 1.1V and peak SIMD energy efficiency of 494GOPS/W at 300mV, 50 (degrees) C."