IDF Fall 2007, part 2-- Process technology

Glaskowsky relates details on process technology from an IDF press briefing

I'm in a press briefing here at IDF covering Intel's 45nm and 32nm manufacturing processes.

Intel's tick-tock product schedule keeps moving along. The latest tick is Penryn; next year comes the tock of Nehalem. Both these chips are from Intel's 45nm process.

Stressing its environmental awareness, Intel stresses that these 45nm chips are lead-free. By the end of 2008, Intel will transition to a halogen-free packaging technology for its 45nm processors.

More details of the 45nm process will be presented at the 2007 International Electron Devices Meeting (IEDM) in December.

Intel projects that 45nm processors will begin to out-ship 65nm processors in 3Q08, or about a year after the first 45nm parts were shipped.

The 32nm SRAM wafer displayed in the morning's keynote was built on what Intel calls its P1268 process, due for full production in 2009. As I said in my keynote post, this chip has 291 million bits and over 1.9 billion transistors. Each SRAM cell, which stores one bit, covers 0.182 square microns. The whole chip is just 118 square millimeters in size. On the same wafer, Intel tested other circuits it needs for future microprocessors.

That's about it for this session. Back later with more updates from IDF.

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About the author

    Peter N. Glaskowsky is a computer architect in Silicon Valley and a technology analyst for the Envisioneering Group. He has designed chip- and board-level products in the defense and computer industries, managed design teams, and served as editor in chief of the industry newsletter "Microprocessor Report." He is a member of the CNET Blog Network and is not an employee of CNET. Disclosure.

     

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