Developing chip muscle through strain

Processor powerhouses IBM and Intel are set to reveal their plans to use the "strained silicon" technique to build faster, power-efficient chips--and maybe break free of Moore's Law.

The strains of creating faster processors will get an airing among chipmakers next week.

Read about chip advances
Researchers and design engineers from IBM and Intel will present papers at the International Electron Devices Meeting (IEDM) next week that detail their work on "strained silicon," a manufacturing technique that promises to boost processor performance by up to 20 percent.

The San Francisco convention, one of the principal events for semiconductor designers, will feature a keynote speech by Intel Chairman Andy Grove as well as presentations from Sony, Samsung, Pennsylvania State University and the Massachusetts Institute of Technology, among others.

Strained silicon--like double-gate and triple-gate transistors, silicon on insulator (SOI) and other new design ideas coming to the fore--should allow chipmakers to maintain the performance curve established by Moore's Law, the semiconductor industry principle stating that manufacturers will double the number of transistors on chips every two years.

Typically, increasing the number of transistors (a trick accomplished by shrinking them) leads to higher performance and new capabilities for processors. But this approach also leads to escalating levels of energy consumption, among other problems--spurring designers to come up with creative solutions.

"There is a fundamental change in the methodology of progress," said Bernard Meyerson, chief technology officer of IBM's Technology group, which includes IBM Microelectronics. "You are going to work a hell of a lot harder to stay on a predictive curve...You are actually going to have to increase the innovation in materials."

This change in perspective means that deep research in materials and transistor design--especially the kind of research that IBM and Intel researchers specialize in--will become much more important in the future. The concept of strained silicon has been around for 30 years, but it only recently moved to the center of concern for chip designers.

Strained silicon--which will appear in Intel's Prescott chip next year--stretches the distances between the silicon atoms in transistors, the tiny on/off switches that form the basis of a chip. Moving these atoms slightly farther apart reduces the atomic forces that interfere with the movement of electrons through the transistors, leading to better performance and lower energy consumption for the chip.

In strained silicon, the atoms are stretched by inserting germanium atoms into the chip's silicon lattice. Another chipmaking technique involves adding a layer of silicon-germanium into the transistor bed. The two technologies are conceptually related--but different--and can be used in the same chip.

Intel's Grove is expected to touch on some of the hurdles facing chip designers during an IEDM keynote address scheduled for Tuesday. The speech is expected to cover the semiconductor industry's approach to past problems and its future challenges, including the use of new materials and the introduction of new transistor designs, an Intel representative said.

R&D rivalry
The convention will also mark the latest episode in the ongoing research and development battle between IBM and Intel. The two companies are largely the leaders in the field, but certainly not friends. IBM often points out that it is responsible for many semiconductor design breakthroughs, such as using copper rather than aluminum wire to connect circuits. Intel counters that it sells far more chips than IBM does.

As previously reported, IBM researchers are slated to present three papers on their efforts to build a double-gate transistor using the Fin Field Effect Transistor (Fin-Fet) approach. These transistors could be used to control power consumption, among other things, in future chips.

IBM Microelectronics also plans to unveil a paper on its new 350GHz communications transistor, announced last week. Meanwhile, IBM Research has lined up a paper on 3D circuit designs, which use two or more layers of transistors.

For its part, Intel discussed its take on multiple-gate transistors at its Intel Developer Forum this fall. The chip powerhouse looks likely this time to concentrate on discussing its forthcoming 90-nanometer manufacturing process, which pairs strained silicon and other new materials to boost performance. It will present separate papers on the process for PC chips and for communications processors.

But beyond that, the company is particularly proud of its ability to implement strained silicon for a low cost. The technology is a "key part of our strategy now and one of the elements that we use to extract more performance out of our transistors," said Mark Bohr, an Intel research fellow specializing in manufacturing technology. "It's going to go into manufacturing next year and in a cost-effective manner. That's a significant accomplishment."

The use of strained silicon raises chip manufacturing costs by 1 or 2 percent for a performance gain of 10 percent to 20 percent, Bohr said.

IBM looks likely to bring strained silicon to market later than Intel. Initially, the company said it would introduce strained silicon in 2003. However, it has since decided it can reach the performance levels it needs at the next process step--the 90-nanometer level--using existing technologies such as silicon on insulator.

IBM now plans to introduce strained silicon in its 65-nanometer manufacturing technology, which lies two chip generations and about three years in the future, said Jeff Welser, a project manager at IBM Microelectronics.'s Michael Kanellos contributed to this report.

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